Although the timing has entered 2021, the well-known "Moore's Law" in the semiconductor industry is still the main driving force that dominates the global integrated circuit application sector market and engineering manufacturers, and continues to move forward.
Traditionally, Moore’s Law is built on process scaling technology. As the result of various wafer fabs (IDM, Foundry) continuously advancing smaller and higher-level processes, the number of transistors per unit chip area is every two years. It is expected to show a multiplication result; from 1965 to 2021, for a total of 66 years, it is estimated that the number of transistors should increase to 8.6 billion today. This is in line with the application processor (Application Processor) of Apple's latest smartphone iPhone 12. : AP)—A14, the number of transistors reaches 11.8 billion, which is not far away.
Four keys to efficiency, power consumption, area, and price chip beyond Moore's Law
However, the miniaturization of the process alone can no longer meet the performance improvement requirements expected by the traditional Moore's Law. Instead, More than Moore's Law is used. The considerations required for a chip are no longer limited to focusing on transistors. The key size and quantity include: PPAC four items-namely Performance (efficiency), Power (power consumption), Area (chip area), Cost (price).
In order to double the number of transistors per IC chip area, the standard unit height of the transistor is designed, so the miniaturization process is also followed. In the packaging process, the traditional packaging process has been transformed into an advanced 2.5D and 3D heterogeneous integrated packaging process, which greatly improves chip performance, but at the same time, it also increases the technological complexity of the packaging process.
In order to eliminate the need for computing data to flow in and out of the microprocessor frequently, and waste data transfer time and operating power consumption, the computer architecture introduces the concept of in-memory computing (IMC) to improve the computing of the microprocessor chip. efficacy.
In the past nearly half a century, the research and development process of IC logic process in the global industry has been led by the first vertically integrated manufacturing company (IDM) Intel (Intel); in the 1990s, many contending and fierce competition, and the market competition is active. Challenge Intel’s unshakable dominance. After years of market competition and elimination of the superior and the inferior, it has finally become one in recent years.
Although the industry competition of logic process has stopped a little, another more fierce competition battlefield-the development of advanced packaging technology, has been launched many years ago, and all major international wafer manufacturers (IDM, Foundry) have their own research and development processes. The solutions have been gradually implemented in its high-end foundry service products.
For example: Foveros and Embedded Multi-Die Interconnect Bridge (EMIB) proposed by Intel, Integrated Package-on-Package (iPOP) and fan Fan-Out Panel Level Packaging (FOPLP) & FOPLP-PoP, as well as the 3D Fabric platform proposed by TSMC (TSMC, 2330) (including SoIC, InFO, CoWoS, etc.).
Whether the innovation of the semiconductor industry can advance by advanced packaging is the key to success or failure
According to TrendForce statistics, in the first quarter of 2021, the top ten global packaging and testing vendors' revenue reached 7.174 billion US dollars, an annual increase of 21.5%. The main growth momentum comes from the improvement of 5G, AI and IoT application technologies, which gradually drive the demand for terminal products such as mobile phones, consumer electronics, vehicles and servers. In addition, due to the lack of semiconductor production capacity due to the active stocking of global terminal manufacturers, packaging and testing manufacturers directly responded by increasing prices to meet market demand and ensure profits at the same time. Major packaging and testing plants respond to the increasing market demand , And gradually increase capital expenditures, and successively embark on related plant expansion plans. In addition, the current AiP module manufacturers that provide 5G millimeter wave mobile phones mainly still dominate the market with Qualcomm, and they have successively launched fourth-generation products such as QTM545, which will be supplied to related terminal manufacturers. At present, related AiP packaging and testing OEM mainly commissioned ASE to perform post-processing, which further drove its first quarter revenue performance.
The global "advanced packaging" market, which is growing at an accelerating speed, is continuing to attract giants from all sectors of the semiconductor supply chain, including: TSMC, Intel, Samsung, Amkor, ASE ) And other semiconductor giants in different fields are active in the market and fully grasp the value of market development. Advanced packaging technology has now become an important key to the innovation and advancement of the semiconductor industry. It continues to promote industry participants to explore new areas, and it has also become an important key to bridging the development gap between IC chips and PCBs.
The development of advanced packaging technology is currently shifting from the original packaging substrate platform application to a higher-level technology level of integrated packaging between IC chips. The development and transformation of this industry is precisely for semiconductor giants such as TSMC, Intel, and Samsung. The best opportunity platform for their technical strength, but also helps them to become the global semiconductor industry, the leading group of the new generation of advanced IC packaging technology. Especially in the development of innovative advanced packaging platforms-from the original fan-out (InFO) packaging, to the 2.5D Si interposer (CoWoS), and up to the 3D SoIC stage, TSMC has become a leading manufacturer in the above-mentioned fields.
The fastest growing advanced packaging platform 3D/2.5D stacking and fan-out
The advanced IC packaging process has become an important key to the continuous innovation and forward development of the global semiconductor industry. It is very important to shorten the physical distance between the IC chip and the PCB in the three-dimensional stacking process.
The semiconductor industry is continuing to develop new-generation products that can be applied to the miniature technology blueprint and functional blueprint. Although there are only three major semiconductor wafer fab participants in the overall market, and the process of miniaturization seems to have slowed down There are signs, but the process miniaturization development blueprint is expected to continue to seven-nanometer and higher-level advanced processes.
As far as the realization of the functional blueprint is concerned, the use of heterogeneous integration technology of wafer manufacturers and the strong support of advanced IC packaging technology will therefore become even more important. Indeed, advanced semiconductor IC packaging technology can further increase the value of semiconductor products by increasing functionality and continuously improving performance, and at the same time by reducing costs.
Regarding the high-end and low-end markets of IC chip process applications, the industry is actively developing various multi-chip packages, such as system-in-package (SiP), 2.5D Si interposer, in areas such as consumer demand, performance, and specialized applications. (CoWoS) packaging, fan-out (InFO) packaging, the application of these different packaging processes will meet the relevant functionality required for integration with heterogeneous IC chips, as well as faster time to market and other customer order requirements.
In terms of various advanced IC packaging technologies, flip-chip packaging (FC) will account for approximately 83% of the global total market revenue in 2019. However, it is estimated that by 2025, its market share will further decline to about 77%; however, the market share of 3D stacking and fan-out packaging technology will increase by 5% from 2015 to 2025. The growth reached 10% and 7% respectively. 3D stacking and fan-out packaging technologies will continue to grow at 21% and 16%, respectively, which impresses market participants, steadily increasing their adoption rates in various applications.
The growth of the global semiconductor 3D IC stacking market is mainly composed of 3D memory-high bandwidth memory (HBM), 3D DDR DRAM, 2.5D interposer-based bare chip area and heterogeneous integration, 3D NAND and stacked CIS, Foveros, Driven by packaging technologies such as 3D SoC.
Thanks to the entry of new entrants from different business models, the overall fan-out packaging market is also expected to see strong growth.
The fan-in wafer-level packaging (WLP) technology market is dominated by mobile device applications, with a CAGR of 3.2% from 2019 to 2025. Although the embedded chip market is relatively small, it is expected that the CAGR will reach 18% in the next five years, driven by the simultaneous driving of the telecommunications and infrastructure, automotive and mobile device application markets.